Hardware Description Languages (HDLs), such as the Very high speed integrated circuit Hardware Description Language (VHDL) or Verilog, are text-based approaches to digital logic design through behavioral and/or structural description of design elements. HDL can be used to design: (1) a programmable logic device (PLD), such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD); (2) a mask programmable device, such as a hardwired pin grid array (PGA), application-specific standard product (ASSP) or application specific integrated circuit (ASIC); (3) a system formed from selected electronic hardware components; or (4) any other electronic device. The HDL-based design methodology requires the user to describe the behavior of a system, which can then be simulated to determine whether the design will function as desired. The design is then synthesized to create a logical network list (“netlist”) that can be implemented within a particular device.
Hardware designers currently develop designs and the respective test benches by hand. Designers simulate their designs with the test benches to make sure the design functions as intended. Next, the design is realized via a synthesis process, and a post-synthesis implementation netlist is exported that includes the functional description and timing information for the hardware. During the testing and synthesis process, the designer is looking for potential design errors and problems. The designer is also looking for ways to improve performance (e.g., speed) and reduce costs (e.g., device area).
With many HDLS, when conditional logic is not completely filled out, synthesis of the HDL code will produce a latch. Such latches are commonly referred to as inferred or implied latches. Inexperienced designers will often code conditional logic that results in inferred latches. Such unintentional inferred latches result in slower, possibly incorrect hardware designs. In addition, inferred latches cause the design to take more hardware area than the design would without the extra inferred latches. As such, inferred latches typically baffle novice designers until they determine the root cause.
Experienced designers on the other hand, may intentionally code inferred lathes when using if-then statements, for example, but may unintentionally code inferred latches for other structures, such as case statements, for example. Also, in large case statements having many assignments for each case, designers can easily overlook a single assignment for a particular signal, resulting in an unintentional inferred latch. Depending on the sophistication and depth of the test bench, even the experienced designer may not detect the unintentional latches.
The traditional way to avoid inferred latches is to verify the design with the test bench. The designer simulates the design by taking the HDL source code and the test bench into a simulator. To detect inferred latches, the designer needs to fully understand the manner in which HDL should act, and needs to code extensive test benches that still can easily overlook inferred latch problems.
Accordingly, it would be both desirable and useful to provide method and apparatus for automatically eliminating inferred latches created by HDL code.